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W24129A 16K x 8 HIGH-SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W24129A is a high-speed, low-power CMOS static RAM organized as 16384 x 8 bits that operates on a single 5-volt power supply. This device is manufactured using Winbond's high performance CMOS technology.
FEATURES
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High-speed access time: 12/15 nS (max.) Low-power consumption:
-
* * *
All inputs and outputs directly TTL compatible Three-state outputs Available packages: 28-pin 300 mil SOJ and skinny DIP
Active: 400 mW (typ.)
* *
Single +5V power supply Fully static operation
PIN CONFIGURATION
BLOCK DIAGRAM
VDD VSS
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD WE A13 A8 A9 A11
A0 . . A13
DECODER
CORE ARRAY AR AY R
CS OE WE CONTROL DATA I/O I/O1 . . I/O8
OE A10
CS I/O8 I/O7 I/O6 I/O5 I/O4
PIN DESCRIPTION
SYMBOL A0-A13 I/O1-I/O8 CS WE OE VDD VSS DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Input Write Enable Input Output Enable Input Power Supply Ground Publication Release Date: July 1995 Revision A2
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W24129A
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Supply Voltage to VSS Potential Input/Output to VSS Potential Allowable Power Dissipation Storage Temperature Operating Temperature RATING -0.5 to +7.0 -0.5 to VDD +0.5 1.0 -65 to +150 0 to +70 UNIT V V W C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
TRUTH TABLE
CS H L L L OE X H L X WE X H H L MODE Not Selected Output Disable Read Write I/O1-I/O8 High Z High Z Data Out Data In VDD CURRENT ISB,ISB1 IDD IDD IDD
OPERATING CHARACTERISTICS
(VDD = 5V 5%, VSS = 0V, TA = 0 to 70 C)
PARAMETER Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Power Supply Current
SYM. VIL VIH ILI ILO VOL VOH IDD
TEST CONDITIONS VIN = VSS to VDD VI/O = VSS to VDD, CS = VIH or OE = VIH or WE = VIL IOL = +8.0 mA IOH = -4.0 mA CS = VIL, I/O = 0 mA Cycle = MIN 12 15
MIN. -0.5 +2.2 -10 -10 2.4 -
TYP. -
MAX. +0.8 VDD +0.5 +10 +10 0.4 160 150 30 5
UNIT V V A A V V mA mA mA mA
ISB ISB1
CS = VIH Cycle = MIN, Duty = 100% CS VDD -0.2V
Note: Typical characteristics are at VDD = 5V, TA = 25 C.
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W24129A
CAPACITANCE
(VDD = 5V, TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance Input/Output Capacitance
SYM. CIN CI/O
CONDITIONS VIN = 0V VOUT = 0V
MAX. 8 10
UNIT pF pF
Note: These parameters are sampled but not 100% tested.
AC TEST CONDITIONS
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V to 3V 5 nS 1.5V CL = 30 pF, IOH/IOL = -4 mA/8 mA CONDITIONS
AC TEST LOADS AND WAVEFORM
R1 480 ohm R1 480 ohm 5V OUTPUT 30 pF Including Jig and Scope R2 255 ohm 5V OUTPUT 5 pF Including Jig and Scope R2 255 ohm
(For TCLZ, TOLZ , TCHZ, TOHZ , TWHZ , TOW)
3.0V
90% 10% 5 nS
90% 10% 5 nS
0V
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Publication Release Date: July 1995 Revision A2
W24129A
AC CHARACTERISTICS
(VDD = 5V 5%, VSS = 0V, TA = 0 to 70 C)
Read Cycle
PARAMETER Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Disable to Output in High Z Output Hold from Address Change These parameters are sampled but not 100% tested. SYM. TRC TAA TACS TAOE TCLZ TOLZ TCHZ TOHZ TOH W24129A-12 MIN. 12 3 0 3 MAX. 12 12 6 6 6 W24129A-15 MIN. 15 3 0 3 MAX. 15 15 7 7 7 nS nS nS nS nS nS nS nS nS UNIT
Write Cycle
PARAMETER Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write These parameters are sampled but not 100% tested. SYM. TWC TCW TAW TAS TWP CS, WE TWR TDW TDH TWHZ TOHZ TOW W24129A-12 MIN. 12 10 10 0 10 0 7 0 0 MAX. 7 7 W24129A-15 MIN. 15 13 13 0 10 0 9 0 0 MAX. 8 8 nS nS nS nS nS nS nS nS nS nS nS UNIT
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W24129A
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
TRC Address TOH DOUT TAA TOH
Read Cycle 2
(Chip Select Controlled)
CS TACS DOUT TCLZ TCHZ
Read Cycle 3
(Output Enable Controlled)
T RC Address TAA OE TAOE TOLZ CS TACS DOUT TCLZ T CHZ TOHZ TOH
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Publication Release Date: July 1995 Revision A2
W24129A
Timing Waveforms, continued
Write Cycle 1
(OE Clock)
TWC Address T WR OE
TCW CS TAW WE TAS TOHZ D OUT TDW DIN TDH (1,4) TWP
Write Cycle 2
(OE = VIL Fixed)
T WC Address TCW CS TAW WE TAS TWP TWHZ (1,4) TOH (2) TOW (3) TWR
DOUT
TDW DIN
TDH
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
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W24129A
ORDERING INFORMATION
PART NO. ACCESS TIME (nS) 12 15 12 15 OPERATING CURRENT MAX. (mA) 160 150 160 150 STANDBY CURRENT MAX. (mA) 5 5 5 5 PACKAGE
W24129AK-12 W24129AK-15 W24129AJ-12 W24129AJ-15
Notes:
300 mil skinny DIP 300 mil skinny DIP 300 mil SOJ 300 mil SOJ
1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
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Publication Release Date: July 1995 Revision A2
W24129A
PACKAGE DIMENSIONS
28-pin P-DIP Skinny
Symbol
Dimension in Inches Dimension in mm
Min. Nom.
0.010 0.125 0.016 0.058 0.008 0.130 0.018 0.060 0.010 1.388 0.300 0.283 0.090 0.120 0 0.330 0.350 0.310 0.288 0.100 0.130
Max.
0.175
Min. Nom.
0.25
Max.
4.45
D
28 15
E1
A A1 A2 B B1 c D E E1 e1 L
a
0.135 0.022 0.064 0.014 1.400 0.320 0.293 0.110 0.140 15 0.370 0.055
3.18 0.41 1.47 0.20
3.30 0.46 1.52 0.25 35.26
3.43 0.56 1.63 0.36 35.56 8.13 7.44 2.79 3.56 15
7.62 7.19 2.29 3.05 0 8.38
7.87 7.32 2.54 3.30
1
14
eA S Notes:
8.89
9.40 1.40
S
E
Base Plane
A A2 L B B1 e1 A1
c
Mounting Plane
a eA
1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec.
28-pin Small Outline J Band
Symbol
Dimension in Inches Dimension in mm
Min. Nom.
0.027 0.095 0.026 0.016 0.008 0.100 0.028 0.018 0.010 0.710 0.295 0.044 0.245 0.327 0.077 0.300 0.050 0.265 0.337 0.087
Max.
0.140
Min. Nom.
0.69
Max.
3.56
28
15
E
HE
1
14
A A1 A2 b1 b c D E e e1 HE L S y
Notes:
0.105 0.032 0.022 0.014 0.730 0.305 0.056 0.285 0.347 0.097 0.045 0.004
2.41 0.66 0.41 0.20
2.54 0.71 0.46 0.25 18.03
2.67 0.81 0.56 0.36 18.54 7.75 1.42 7.24 8.81 2.46 1.14 0.10
7.49 1.12 6.22 8.31 1.96
7.62 1.27 6.73 8.56 2.21
0
10
0
10
D c A2 A L c e A1 y e1
s Seating Plane
b b1
1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimension D & E include mold mismatch and are determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec. should be based on final visual inspection spec.
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W24129A
Headquarters
No. 4, Creation Rd. III,
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792647 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505
Note: All data and specifications are subject to change without notice.
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Publication Release Date: July 1995 Revision A2

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